The present invention relates to the manufacture of integrated circuits. More particularly, the present invention provides a technique for forming substrates using a novel edge engineering technique. This invention is illustrated using, for example, silicon-on-insulator ("SOI") wafers, but can be applied to other types of substrates such as bulk substrates, patterned substrates, multi-layered substrates, and others.
Integrated circuits are fabricated on chips of semiconductor material. These integrated circuits often contain thousands, or even millions, of transistors and other devices. In particular, it is desirable to put as many transistors as possible within a given area of semiconductor material because more transistors typically provide greater functionality, and a smaller chip means more chips per wafer and lower costs. From the development of the integrated circuit at Fairchild Semiconductor by Robert Noyce and Jack Kilby at Texas Instruments to modern day times, industry has always attempted to fabricate more and more devices on a given area of silicon.
Some integrated circuits are fabricated on a slice or wafer, of single-crystal (monocrystalline) silicon, commonly termed a "bulk" silicon wafer. Devices on such "bulk" silicon wafer typically are isolated from each other. A variety of techniques have been proposed or used to isolate these devices from each other on the bulk silicon wafer, such as a local oxidation of silicon ("LOCOS") process, trench isolation, and others. These techniques, however, are not free from limitations. For example, conventional isolation techniques consume a considerable amount of valuable wafer surface area on the chip, and often generate a non-planar surface as an artifact of the isolation process. Either or both of these considerations generally limit the degree of integration achievable in a given chip. Additionally, trench isolation often requires a process of reactive ion etching, which is extremely time consuming and can be difficult to achieve accurately.
An approach to achieving very-large scale integration ("VLSI") or ultra-large scale integration ("ULSI") uses a semiconductor- or silicon-on-insulator ("SOI") wafer. An SOI wafer typically has a layer of silicon on top of a layer of an insulator material. A variety of techniques have been proposed or used for fabricating the SOI wafer. These techniques include, among others, growing a thin layer of silicon on a sapphire substrate, bonding a layer of silicon to an insulating substrate, and forming an insulating layer beneath a silicon layer in a bulk silicon wafer, which is commonly termed SIMOX. In an SOI integrated circuit, essentially complete device isolation is often achieved using conventional device processing methods by surrounding each device, including the bottom of the device, with an insulator. An advantage SOI wafers have over bulk silicon wafers is that the area required for isolation between devices on an SOI wafer is less than the area typically required for isolation on a bulk silicon wafer.
SOI offers other advantages over bulk silicon technologies as well. For example, SOI offers a simpler fabrication sequence compared to a bulk silicon wafer. Devices fabricated on an SOI wafer may also have better radiation resistance, less photo-induced current, and less cross-talk than devices fabricated on bulk silicon wafers. Many problems, however, that have already been solved regarding fabricating devices on bulk silicon wafers remain to be solved for fabricating devices on SOI wafers.
That is, numerous limitations exist in the manufacture of SOI wafers. In general, some techniques for fabricating SOI can produce SOI wafers with substantially defect free layers having relatively low thickness variation, but these techniques often produce SOI wafers in relatively low yield and at high cost, as compared to bulk wafers. Other techniques can produce high yields. These techniques, however, often produce poor quality films.
From the above, it is seen that an improved technique for manufacturing a substrate such as, for example, an SOI wafer and others is highly desirable.